|FMC LPC Pin Header DS#T0011 REV 2022/18/01 PDF version (coming soon), HTML version|
|Pin Header Board for Low-Pin CountFMC Connectors|
The photos below show the bottom side with LPC mezzanine card connector (MC-LPC-10) and top side with pin headers (2.54 grid) and SMA connectors.
The FMC pin header board was developed to make the high density FMC connector of many FPGA boards easily accessible. In many applications easily pluggable connections are required to process and check the digital signals. The use of 2.54 mm pin headers is very common. Thus, the FMC pin header board enables a variety of applications for digital signal processing and testing. The total number of 68 user signals (LAxx_P/N), 4 user clocks (CLKx_M2C_P/N) and 3 voltage rails (VADJ, 3P3V and 12PV0) from the carrier card connector are routed to the 2.54 mm pin grid on top of the adapter board. In addition, the high-speed data lanes (multi-gigabit transceivers) are easily accessible via SMA connectors on the edge of the PCB. Finally, the board allows complete interconnection of all signals from the FMC connector.
|2. Application information
Fig. 1 shows a typical application of the FMC pin header adapter where two carrier boards are connected together. Loose cables can be used for digital signals in the range of several 10 MHz. Fig. 1: Board-to-board interconnection with the FMC LPC pin header board. For high-speed data connections between two boards, the SMA connectors should be used. Data rates of several gigabits per second are common and depend on the FPGA of the carrier board. Fig. 2 below shows the test setup for measuring the maximum datarates of the Pin-Header Board with a loopback configuration. The SMA cables are about 50 cm long. Fig. 2: Loopback connection with the FMC LPC pin header board. The SMA connectors of the Pin Header Board have been tested with datarates up to 8.5 Gbps without errors. Even faster connections are possible, but then the cable quality and length are more important than the characteristics of the board itself. Fig. 3 and fig. 4 show the results of an eyescan with an Xilinx Zynq Ultrascale+ FPGA. Fig. 3: Eyescan of the loopback connection with a datarate of 5.94 Gbps. Fig. 4: Eyescan of the loopback connection with a datarate of 8.5 Gbps.
|3. Electrical data (pin description)
3.1 Pinout of the 2.54 mm pin headers Fig. 5 and tab. 1 show the connections of the FMC signals on the pin header connectors J1, J2, and J3. Fig. 5: Pin assignments of the FMC LPC pins to the pin headers J1, J2, and J3.
3.2 SMA Connectors for Gigabit transceivers The FMC LPC connector has one multi-gigabit transceiver data pair (DP0_M2C_P/N and DP0_M2C_P/N) and a corresponding differential clock input (GBTCLK0_M2C_P/N). These six signals are all routed to the SMA connectors. The circuitry is shown in Fig. 6. Fig. 6: SMA connectors with corresponding Gigabit transceiver ports on the FMC connector (schematic view). Fig. 7 shows the signal assignemnts, but the designators of the signals can be also read on the circuit board.. Fig. 7: SMA connectors and their associated Gigabit transceiver signals.
3.3 SMA Connector for clock IO One of the FMC connector pins CLK0_M2C_P (pin H4) or CLK1_M2C_P (pin G2) can be routed a separate SMA connector on the board edge. A zero ohm resistor determines which clock signal will be used. The clock signals are also routed to the 2.54 mm pin headers J1 and J2. By default, the signal CLK0_M2C_P (CLK0_P) is selected by resistor R1 (see fig. 8 and fig. 9). Fig. 8: Clock selection circuit with a zero ohm resistor. The SMA connector can be used as clock input or clock output. Fig. 9: Resistors R1 and R2 for selecting the clock signal CLK0_M2C_P (Pin H4) or CLK1_M2C_P (Pin G2) of the SMA connector. The size of the resistor is 1206 and can be easily soldered by hand. The SMA connector (designator CLK_IO) for the dedicated clock signal is on the left side of the board (front view, see fig. 10). Fig. 10: The SMA connector for the dedicated clock input/output is on the left side of the board.
3.4 FMC FRU EEPROM The EEPROM for storing FMC FRU (field replaceable unit) information is an M24C02 with 2 Kbit (256 Byte). The FRU record determines the voltage on the VADJ rail of the FMC connector. By default, the FRU EEPROM is programmed to request 3.3 V from the carrier board. Further, the memory stores the board information such as manufacturer name and product number. The devices can be read and written by the I2C interface of the FMC connector. The Pin Header board includes 4K7 pull-up resistors on the SCL and SDA signal lanes. The I2C address of the M24C02 is defined by the GA0 and GA1 pins of the FMC connector in accordance with the ANSI/VITA57.1 standard. Fig. 11: The M24C02 EEPROM stores the FMC FRU information record.
|4. Mechanical data
The board outline is defined by the ANSI/VITA 57.1 standard for single width FMC modules. It has a shortened length of the standard size and fits into any ANSI/VITA 57.1 compliant carrier board. The exact dimensions are given in fig. 12.Fig. 12: Mechanical drawing of the FMC LPC Pin Header Board. The mounting holes are plated but have no electrical connection. Their sizes and positions are in accordance with ANSI/VITA 57.1 single width FMC modules.
|5. Ordering information
The FMC LPC Pin Header Board can be ordered at various online market places, or you can request a quotation by sending an e-mail to email@example.com.
Tab. 5: Assembly variants of FMC LPC Pin Header board with product numbers and market places.
|6. Ressources  Schematics: FMC_PINHEADER_BOARD_SCHEMATICS.pdf  PCB drawings: FMC_PINHEADER_BOARD_PCB_LAYERS.pdf  Mechanical dimensions: FMC_PINHEADER_BOARD_MECHANICAL_DIMENSIONS.pdf  Github repository: https://github.com/FMCHUB/FMC_LPC_PINHEADER|
|7. Document history Document number: DS#T0011 Version history: 2022/01/18: fixed pin assignments in Tab. 1 2020/11/02: Initial release|
|8. Imprint Name and registered office of the company: IAM Electronic GmbH Bucksdorffstr. 43 04159 Leipzig Germany Contact: Phone: +49 341 26496031 E-Mail: firstname.lastname@example.org Chief Executive Officer: Dr. Philipp Födisch Commercial register: Register court: Amtsgericht Leipzig Register number: HRB 34071 Value Added Tax Identification Number: DE313797981|